Verification Engineer - SoC


Sep 11, 2018
San Jose, California



Verification Engineer - SoC
San Jose, CA
6+ Months Contract 

Job Description
This is going to be SoC verification, but someone who has analog experience, because they will be debugging with the analog team.

Hands-on experience on
·         Embedded system Verification methodology
·         General DV concepts on CPU sub-system and peripheral/CPU HW/SW development flow
·         C/Assembly, Verilog and system Verilog languages
·         Strong debugging skills on tools like Verdi, VCS and DVE
·         Strong test bench modeling experiments in sensing field
·         Deep knowledge on I2C/SPI, memory interfaces
·         Deep knowledge on SCAN/mBIST flow, and mixed signal simulation requirements.
·         Deep knowledge on coverage analysis, rich experience on SVA or PSL  it is preferred that candidate has experience on static/formal verification flow 
e.g. clock domain crossing, reset domain crossing
·         CPU/system verification experience with knowledge on C/assembly language and firmware tool chain setup
·         Experience on Cadence Conformal/Synopsys Spyglass(Atrenta)/Mentor Questa tool and be familiar with clock domain crossing verification method
·         Rich experience on Coverage-Driven Verification Methodology or SVA

 It is better that candidates have experience to verify I3C and SPI design


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